Technology trends and Electromagnetic Compatibility of Integrated Circuits
9:20am-10:00am, October 21
International YuanZheng Hotel ZJU
Etienne SICARD from INSA, University of Toulouse, France
Prof. Sicard is currently a professor in the Department of Electrical and Computer Engineering at INSA, an engineering school part of the University of Toulouse, France. He is associate researcher at IRIT laboratory, and research director at LURCO laboratory. Granted the Monbusho scholarship award, he conducted post-doctoral studies at Osaka University, Japan (1988-1989). He received a B.S degree and a PhD in Electrical Engineering from the University of Toulouse, France, in 1984 and 1987 respectively. He was elected Distinguished IEEE Lecturer of the EMC society for 2006 -2007. Professor Sicard has authored or co-authored over 20 books, 10 commercial software packages (Microwind, IC-EMC, vocalab, Diadolab) and more than 250 technical papers in a many areas of electrical engineering, including nano-scale CMOS technology, integrated circuit design automation and digital signal processing for speech therapy. He is the founder of EMC Compo international workshop (www.emccompo.org) focused on Electromagnetic Compatibility of Integrated Circuits.
Plenary Talk II
Antenna-in-Package (AiP) Technology：The Key to the Success of Millimeter-wave 5G
10:00am-10:40am, October 21
International YuanZheng Hotel ZJU
ZHANG Yueping FIEEE from Nanyang Technological University, Singapore
Wireless communications advance rapidly towards the fifth generation (5G), which promises to transform the way we interact with our world over the next several years by enabling fast response time, Gbps delivery, and the Internet of Things (IoT). To take the 5G vision a reality, antenna-in-package (AiP) technology has been recognised as the key to the success of 5G, especially at millimetre-wave frequencies. In this talk, I shall first discuss four basic aspects of AiP technology including design, fabrication, testing, and applications. I shall then give an AiP example designed in an advanced fan-out wafer level packaging for 5G user equipment. Finally, I shall draw the conclusion and identify future direction to further advance AiP technology.
ZHANG Yueping is a full Professor with the School of Electrical and Electronic Engineering at Nanyang Technological University, Singapore, a Distinguished Lecturer of the IEEE Antennas and Propagation Society (IEEE AP-S), a Member of the IEEE AP-S Paper Award Committee, and a Fellow of IEEE.
Prof. ZHANG was a Member of the IEEE AP-S Field Award Committee (2015-2017), an Associate Editor of the IEEE Transactions on Antennas and Propagation (2010-2016), and the Chair of the IEEE Singapore MTT/AP joint Chapter (2012). Prof. ZHANG was selected by the Recruitment Program of Global Experts of China as a Qianren Scholar at Shanghai Jiao Tong University (2012). He was awarded a William Mong Visiting Fellowship (2005) and appointed as a Visiting Professor (2014) by the University of Hong Kong.
Prof. ZHANG has published and accepted numerous papers, including two invited and one regular papers in the Proceedings of the IEEE and one invited paper in the IEEE Transactions on Antennas and Propagation. He is probably the first and only Chinese radio scientist who has managed to publish a historical article in an English learned journal such as IEEE Antennas and Propagation Magazine. He holds 7 US patents. He received the Best Paper Award from the 2nd IEEE/IET International Symposium on Communication Systems, Networks and Digital Signal Processing, July 18–20, 2000, Bournemouth, U.K., the Best Paper Prize from the 3rd IEEE International Workshop on Antenna Technology, March 21–23, 2007, Cambridge, U.K., and the Best Paper Award from the 10th IEEE Global Symposium on Millimetre-Waves, May 24–26, 2017, Hong Kong, China. He received the prestigious IEEE AP-S Sergei A. Schelkunoff Prize Paper Award in 2012.
Prof. ZHANG has made pioneering and significant contributions to the development of the antenna-in-package (AiP) technology that has been widely adopted by chipmakers for millimetre-wave applications. His current research interests include the development of antenna-on-chip (AoC) technology and characterization of chip-scale propagation channels at terahertz for wireless chip area network (WCAN).
Joungho Kim FIEEE from KAIST, (Korea Advanced Institute of Science and Technology)
Recently, we are facing a newly emerging technology and industrial transition, named as 4th Industrial Revolution, which is based on artificial intelligence (AI), big data platform, and cloud system. Especially, emergence of artificial intelligence is aided by availability of big data, deep learning algorithms, and high performance GPU computing machines. Accordingly, demands for advanced performance of terabyte/s bandwidth computing performance are rapidly increasing. However, continuously growing gaps between GPU performance and DRAM I/O data bandwidth are becoming the critical barrier to limit the AI computing performance. In order to meet the pressing needs of higher data transfer bandwidth, we are proposing High Bandwidth Memory (HBM) solutions using TSV, Si interposer technologies, and stacked memory architectures.
In this presentation, we will introduce the basic approaches and designs of the terabyte/s bandwidth 2.5D HBM (High-bandwidth Memory Module), which will be useful for artificial intelligent servers. Especially, we will talk about the signal and power integrity design issues, and analysis results of TSV and Si interposer channels, including GPU-DRAM channels, and high-speed serial channels. In addition, we will discuss PDN (power Distribution Network) impedance designs, and decoupling capacitor schemes as well. Then, we will propose next generation HBM architectures using active interposer approaches, and equalization schemes to even increase the bandwidths with lower power consumptions. Finally, we will suggest next generation computer architectures to meet the increasing performance needs of AI serves with reduced power consumptions.
Dr. Joungho Kim received B.S. and M.S. degrees in electrical engineering from Seoul National University, Seoul, Korea, in 1984 and 1986, respectively, and Ph.D degree in electrical engineering from the University of Michigan, Ann Arbor, in 1993. In 1996, he moved to KAIST (Korea Advanced Institute of Science and Technology). He is currently professor at electrical engineering department of KAIST. Since joining KAIST, his research centers on EMC modeling, design, and measurement methodologies of 3D IC, TSV, Interposer, System-in-Package, multi-layer PCB, and wireless power transfer (WPT) technologies. Especially, his major research topic is focused on chip-package-PCB co-design and co-simulation for signal integrity, power integrity, ground integrity, timing integrity, and radiated emission in 3D IC, TSV and Interposer. He has authored and co-authored over 527 technical papers published at refereed journals and conference proceedings. He published a book, “Electrical Design of Through Silicon Via,” by Springer in 2014. Currently, he is the director of Samsung-KAIST Industry Collaboration Center.
Dr. Joungho Kim was Conference chair of IEEE EDAPS 2015 in Seoul. And he was the conference chair of IEEE WPTC (Wireless Power Transfer Conference) 2014, held in Jeju Island, Korea. And he was the symposium chair of IEEE EDAPS Symposium 2008. He is also an associated editor of the IEEE Transactions of Electromagnetic Compatibility. He received Outstanding Academic Achievement Faculty Award of KAIST in 2006, KAIST Grand Research Award in 2008, KAIST International Collaboration Award in 2010, and KAIST Grand Research Award in 2014, respectively. He was appointed as an IEEE EMC society distinguished lecturer in a period from 2009-2011. He received Technology Achievement Award from IEEE Electromagnetic Society in 2010. Currently, he is an IEEE fellow.
Plenary Talk IV
A chronicle of 22 years in microcontroller EMC business
11:40am-12:20am, October 21
International YuanZheng Hotel ZJU
Thomas Steinecke from Infineon Technologies, Germany
EMC on IC level was an emerging topic in the 1990s when system designers in EMC-critical areas like automotive started complaining about too high electromagnetic IC emission which caused them to spend additional money on PCB countermeasures. During that time, several national EMC test setup proposals on IC-level were submitted which finally have been integrated in the international standards IEC 61967 and IEC 62132.
After several years of microcontroller design, I stepped into EMC in the year 1997. I spent a lot of effort on the emission analysis of automotive microcontrollers including design and validation of several test chips. Soon we extended our EMC validation portfolio by establishing immunity test environment. We also recognized the need of developing pre-silicon behavioral emission models for large-scale ICs.
My EMC life was accompanied by many years of fruitful collaboration with other semiconductor vendors, automotive Tier1s and OEMs, universities and research institutes. A highlight in the beginning of the new millennium was the introduction of dynamic voltage and current sensors into CMOS test chips. Following up this collaboration with INSA I stepped into the famous series of EMC Compo conferences founded by our dear friend Etienne Sicard. Over time, we introduced – together with other microcontroller vendors – on-chip EMC optimization measures like improved decoupling concepts, scalable pads and clock modulation.
After ten years of self-driven modeling activities, the first EDA vendor provided a commercial modeling and simulation tool. The benefit of that EDA solution was the layout-based models, thus offering design signoff capabilities. But it did not provide a satisfying solution for very early pre-netlist-based emission feasibility studies. This gap motivated me to create an own tool which allows such studies on SoCs using basic activity data for the functional modules.
Although we advanced quite well on simulating electromagnetic emission of complex ICs, there are still modeling gaps in the area of robustness, meaning DPI and pulse immunity as well as powered ESD.
My countdown for leaving the EMC stage is running. I am sure that our next generation engineers are eager to further disenchant the “black magic” in the EMC domain. EMC-related topics like fail-safe operation of autonomous cars are relying on robust IC designs. Hence immunity simulation of complex ICs will become a high-priority EMC challenge within the next years. I encourage you to dive deeper into this fascinating world of EMC and help to make our products of the future smart and safe.
Thomas Steinecke received his diploma on technical computer science in 1984 from the Technical University of Darmstadt, Germany. In the same year, he joined the Siemens Semiconductor Department in Munich, which spun off as Infineon Technologies in 1999. Mr. Steinecke spent several years in microcontroller design before he became responsible for the electromagnetic compatibility of automotive microcontrollers in 1997. Since then, he researched into emission and susceptibility measurement techniques, chip and package design improvement, modeling and simulation. He published many papers and collaborated with customers, universities and research institutes within several national and international funding projects. His team designed a series of EMC test chips introducing on-chip oscilloscopes for dynamic voltage and current measurements. He developed advanced emission modeling techniques for very large-scale integrated circuits which have meanwhile been adapted in commercial tools. The actual focus of his work is on EMC-optimized design and EMC simulation of automotive microcontrollers in 28 nm technology and beyond.
The 12th International Workshop on the Electromagnetic Compatibility of Integrated Circuits